Domestic High-Performance Computing Chip R&D
Apr 1, 2024
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1 min read
Research Tasks and Assessment Metrics
- Research Task: Investigate core technologies including model partitioning, memory optimization, and parameter communication optimization on large-scale Hygon DPU clusters.
- Assessment Metrics: Apply for 1 software copyright, 2 invention patents, publish 2 academic papers, and train 2 graduate students.
Project Phases
Phase 1: Solution Design (Sep 2024 - Dec 2024)
- Complete hardware platform and framework analysis.
- Determine technical approach for porting and optimization.
Phase 2: Framework Porting (Jan 2025 - Oct 2025)
- Platform setup and basic computing core adaptation.
Phase 3: Performance Optimization (Nov 2025 - Dec 2026)
- Data parallelism, pipeline parallelism, tensor parallelism, and communication optimization.
Phase 4: Application Demonstration (Jan 2027 - Nov 2027)
- Develop toolchain, apply in meteorological domain.
Authors
Tiejun Wang
(he/him)
Team Leader
Received Ph.D. in Computer Application Technology from University of Electronic Science and Technology of China (UESTC) in December 2010. Has undertaken more than 10 research projects including the National Science and Technology Support Program, Sichuan Provincial Science and Technology Program, and projects from State Grid Corporation of China. Awarded two Second-Class Provincial Science and Technology Progress Awards. Published over 20 academic papers (10+ indexed by SCI/EI), authorized 5 national invention patents, obtained 14 software copyrights, and published 4 textbooks.